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w25x64 publication release date: december 19, 2008 - 1 - revision a 64m-bit serial flash memory with 4kb sectors and dual output spi
w25x64 - 2 - table of contents 1 general description................................ ................................................... ................ 4 2 features........................................... ................................................... .......................... 4 3 pin configuration wson 8x6mm ...................... ................................................... ....... 5 4 pin configuration pdip 300mil ..................... ................................................... ........... 5 5 pin description pdip 300mil, wson 8x6............. ................................................... ...... 6 6 pin configuration soic 300mil ..................... ................................................... ........... 6 7 pin description soic 300mil....................... ................................................... .............. 7 7.1 package types ...................................... ................................................... .............. 8 7.2 chip select (/cs) .................................. ................................................... ............... 8 7.3 serial data output (do)............................ ................................................... ............ 8 7.4 write protect (/wp)................................ ................................................... .............. 8 7.5 hold (/hold)....................................... ................................................... .............. 8 7.6 serial clock (clk)................................. ................................................... ............... 8 7.7 serial data input / output (dio) ................... ................................................... .......... 8 8 block diagram...................................... ................................................... ..................... 9 9 functional description ............................. ................................................... .............10 9.1 spi operations ..................................... ................................................... .........10 9.1.1 spi modes .......................................... ................................................... .......................................10 9.1.2 dual output spi.................................... ................................................... ....................................10 9.1.3 hold function ...................................... ................................................... .....................................10 9.2 write protection................................... ................................................... .......11 9.2.1 write protect features ............................. ................................................... ...............................11 10 control and status registers ....................... ................................................... ......12 10.1 status register.................................... ................................................... ........12 10.1.1 busy............................................... ................................................... .........................................12 10.1.2 write enable latch (wel)........................... ................................................... .........................12 10.1.3 block protect bits (bp2, bp1, bp0) ................. ................................................... ...................12 10.1.4 top/bottom block protect (tb) ...................... ................................................... ......................12 10.1.5 reserved bits ...................................... ................................................... ...................................12 10.1.6 status register protect (srp)...................... ................................................... .......................13 10.1.7 status register memory protection.................. ................................................... ..................13 10.2 instructions ....................................... ................................................... ...........14 10.2.1 manufacturer and device identification............. ................................................... .................14 10.2.2 instruction set.................................... ................................................... .....................................15
w25x64 publication release date: december 19, 2008 - 3 - revision a 10.2.3 write enable (06h)................................. ................................................... ................................16 10.2.4 write disable (04h) ................................ ................................................... ...............................16 10.2.5 read status register (05h)......................... ................................................... ........................17 10.2.6 write status register (01h) ........................ ................................................... .........................18 10.2.7 read data (03h) .................................... ................................................... ................................19 10.2.8 fast read (0bh).................................... ................................................... .................................20 10.2.9 fast read dual output (3bh)........................ ................................................... ......................21 10.2.10 page program (02h)................................. ................................................... ..........................22 10.2.11 sector erase (20h)................................. ................................................... .............................23 10.2.12 block erase (d8h).................................. ................................................... .............................24 10.2.13 chip erase (c7h) ................................... ................................................... .............................25 10.2.14 powerdown (b9h) ................................... ................................................... ...........................26 10.2.15 release powerdown / device id (abh) ............... ................................................... ..........27 10.2.16 read manufacturer / device id (90h)................ ................................................... ...............29 10.2.17 jedec id (9fh) ..................................... ................................................... ..............................30 11 electrical characteristics......................... ................................................... ..........31 11.1 absolute maximum ratings ........................... ................................................... ......31 11.2 operating ranges ................................... ................................................... ............31 11.3 powerup timing and write inhibit threshold........ ................................................... ..32 11.4 dc electrical characteristics...................... ................................................... ..........33 11.5 ac measurement conditions .......................... ................................................... ......35 11.6 ac electrical characteristics...................... ................................................... ..........36 11.7 ac electrical characteristics (contd)............. ................................................... .......37 11.8 serial output timing............................... ................................................... .............38 11.9 input timing....................................... ................................................... .................38 11.10 hold timing ........................................ ................................................... ...............38 12 package specification.............................. ................................................... ..............39 12.1 8pin pdip 300mil (package code da) ............... ................................................... .39 12.2 8contact 8x6mm wson (package code ze) ............. .............................................40 12.3 16pin soic 300mil (winbond package code sf)...... ..............................................41 13 ordering information (1) ................................................... .........................................42 14 revision history................................... ................................................... ....................44
w25x64 - 4 - 1 general description the w25x64 (64mbit) serial flash memory provide a storage solution for systems with limited space, pins and power. the 25x series offers flexibility a nd performance well beyond ordinary serial flash devices. they are ideal for code download applicati ons as well as storing voice, text and data. the devices operate on a single 2.7v to 3.6v power supp ly with current consumption as low as 5ma active and 1a for powerdown. all devices are offered in spacesaving packages. the w25x64 array is organized into 32,768 programma ble pages of 256bytes each. up to 256 bytes can be programmed at a time using the page program inst ruction. pages can be erased in groups of 16 (sector erase), groups of 256 (block erase) or the entire chip (chip erase). the w25x64 has 2048 erasable sectors and 128 erasable blocks. the small 4kb sectors allow for greater flexibility in applications that require data and parameter storag e. (see figure 2.) the w25x64 supports the standard serial peripheral interface (spi), and a high performance dual output spi using four pins: serial clock, chip select, ser ial data i/o and serial data out. spi clock frequencies of up to 75mhz are supported allowing e quivalent clock rates of 150mhz when using the fast read dual output instruction. these transfer r ates are comparable to those of 8 and 16bit parall el flash memories. a hold pin, write protect pin and programmable writ e protect, with top or bottom array control feature s, provide further control flexibility. additionally, the device supports jedec standard manufacturer and device identification. 2 features ? family of serial flash memories C w25x64: 64mbit / 8mbyte (8,388,608) C 256bytes per programmable page C uniform 4kbyte sectors / 64kbyte blocks ? spi with single or dual outputs C clock, chip select, data i/o, data out C optional hold function for spi flexibility ? data transfer up to 150-bits / second C clock operation to 75mhz C fast read dual output instruction C autoincrement read capability ? flexible architecture with 4kb sectors C sector erase (4kbytes) C block erase (64kbyte) C page program up to 256 bytes <2ms C more than 100,000 erase/write cycles C more than 20year retention ? low power consumption, wide temperature range C single 2.7 to 3.6v supply C 5ma active current, 1a powerdown (typ) C 40 to +85c operating range ? software and hardware write protection C writeprotect all or portion of memory C enable/disable protection with /wp pin C top or bottom array protection ? space efficient packaging C 8pin pdip 300mil C 16pin soic 300mil C 8pad wson 8x6mm
w25x64 publication release date: december 19, 2008 - 5 - revision a 3 pin configuration wson 8x6-mm figure 1b. w25x64 pad assignments, 8pad wson 8x6m m (package code ze) 4 pin configuration pdip 300-mil figure 1c. w25x64 pin assignments, 8pin pdip (pack age code da)
w25x64 - 6 - 5 pin description pdip 300-mil, wson 8x6 pin no. pin name i/o function 1 /cs i chip select input 2 do o data output 3 /wp i write protect input 4 gnd ground 5 dio i/o data input / output 6 clk i serial clock input 7 /hold i hold input 8 vcc power supply 6 pin configuration soic 300-mil figure 1d. w25x64 pin assignments, 16pin soic 300 mil
w25x64 publication release date: december 19, 2008 - 7 - revision a 7 pin description soic 300-mil pin no. pin name i/o function 1 /hold i hold input 2 vcc power supply 3 n/c no connect 4 n/c no connect 5 n/c no connect 6 n/c no connect 7 /cs i chip select input 8 do o data output 9 /wp i write protect input 10 gnd ground 11 n/c no connect 12 n/c no connect 13 n/c no connect 14 n/c no connect 15 dio i/o data input / output 16 clk i serial clock input
w25x64 - 8 - 7.1 package types at the time this datasheet was published not all pa ckage types had been finalized. contact winbond to confirm availability of these packages before desig ning to this specification. w25x64 is offered in a n 8x6mm wson (package code ze), 16pin plastic 300m il width soic (package code sf) and 300mil dip (package code da). see figures 1ad. package diagrams and dimensions are illustrated at the end of this datasheet. 7.2 chip select (/cs) the spi chip select (/cs) pin enables and disables device operation. when /cs is high the device is deselected and the serial data output (do) pin is a t high impedance. when deselected, the devices power consumption will be at standby levels unless an internal erase, program or status register cycle is in progress. when /cs is brought low the device will be selected, power c onsumption will increase to active levels and instructions can be written to an d data read from the device. after powerup, /cs must transition from high to low before a new instructio n will be accepted. the /cs input must track the vc c supply level at powerup (see write protection an d figure 20). if needed a pullup resister on /cs c an be used to accomplish this. 7.3 serial data output (do) the spi serial data output (do) pin provides a mean s for data and status to be serially read from (shifted out of) the device. data is shifted out on the falling edge of the serial clock (clk) input p in. 7.4 write protect (/wp) the write protect (/wp) pin can be used to prevent the status register from being written. used in conjunction with the status registers block protec t (bp2, bp1, and bp0) bits and status register protect (srp) bits, a portion or the entire memory array can be hardware protected. the /wp pin is active low. 7.5 hold (/hold) the /hold pin allows the device to be paused while it is actively selected. when /hold is brought low, while /cs is low, the do pin will be at high impedance and si gnals on the dio and clk pins will be ignored (dont care). when /hold is brought high, d evice operation can resume. the /hold function can be useful when multiple devices are sharing the sam e spi signals. (see hold function) 7.6 serial clock (clk) the spi serial clock input (clk) pin provides the t iming for serial input and output operations. ("see spi operations") 7.7 serial data input / output (dio) the spi serial data input/output (dio) pin provides a means for instructions, addresses and data to be serially written to (shifted into) the device. data is latched on the rising edge of the serial clock (clk) input pin. the dio pin is also used as an output wh en the fast read dual output instruction is executed.
w25x64 publication release date: december 19, 2008 - 9 - revision a 8 block diagram figure 2. w25x64 block diagram
w25x64 - 10 - 9 functional description 9.1 spi operations 9.1.1 spi modes the w25x64 is accessed through an spi compatible bu s consisting of four signals: serial clock (clk), chip select (/cs), serial data input/output (dio) a nd serial data output (do). both spi bus operation modes 0 (0,0) and 3 (1,1) are supported. the primar y difference between mode 0 and mode 3 concerns the normal state of the clk signal when the spi bus master is in standby and data is not being transferred to the serial flash. for mode 0 the clk signal is normally low. for mode 3 the clk signal is normally high. in either case data input on the dio pin is sampled on the rising edge of the clk. data on the do and dio pins are clocked out on the falling edge of clk. 9.1.2 dual output spi the w25x64 supports dual output operation when usin g the "fast read with dual output" (3b hex) instruction. this feature allows data to be transfe rred from the serial flash memory at twice the rate possible with the standard spi. this instruction is ideal for quickly downloading code from flash to r am upon powerup (codeshadowing) or for applications that cache codesegments to ram for execution. the dual output feature simply allows the spi input pin to also serve as an output during this instruc tion. all other operations use the standard spi interface with single output signal. 9.1.3 hold function the /hold signal allows the w25x64 operation to be paused while it is actively selected (when /cs is low). the /hold function may be useful in cases where the spi data and clock signals are shared with other devices. for example, consider if the page bu ffer was only partially written when a priority int errupt requires use of the spi bus. in this case the /hold function can save the state of the instruction and the data in the buffer so programming can resume where it left off once the bus is available again. to initiate a /hold condition, the device must be selected with /cs low . a /hold condition will activate on the falling edge of the /hold signal if the clk signal is already low. if the clk is not already lo w the /hold condition will activate after the next falling edge of clk. the /hold condition will terminate on the rising edge of the /hold signal if the clk signal is already low. if the clk is not already low the /hold condition will terminate after the next falling edg e of clk. during a /hold condition, the serial data output (do) is high impe dance, and serial data input/output (dio) and serial clock (clk) are ignored. the chip select (/cs) signal should be kept active (low) for the full duration of the /hold operation to avoid resetting the internal logic sta te of the device.
w25x64 publication release date: december 19, 2008 - 11 - revision a 9.2 write protection applications that use nonvolatile memory must take into consideration the possibility of noise and ot her adverse system conditions that may compromise data integrity. to address this concern the w25x64 provides several means to protect data from inadver tent writes. 9.2.1 write protect features ? device resets when vcc is below threshold. ? time delay write disable after powerup. ? write enable/disable instructions. ? automatic write disable after program and erase. ? software write protection using status register. ? hardware write protection using status register an d /wp pin. ? write protection using powerdown instruction. upon powerup or at powerdown the w25x64 will main tain a reset condition while vcc is below the threshold value of v wi , (see powerup timing and voltage levels and figur e 20). while reset, all operations are disabled and no instructions are rec ognized. during powerup and after the vcc voltage exceeds v wi , all program and erase related instructions are fu rther disabled for a time delay of t puw . this includes the write enable, page program, sector era se, block erase, chip erase and the write status register instructions. note that the chip select pi n (/cs) must track the vcc supply level at powerup until the vccmin level and t vsl time delay is reached. if needed a pullup resiste r on /cs can be used to accomplish this. after powerup the device is automatically placed i n a writedisabled state with the status register w rite enable latch (wel) set to a 0. a write enable instr uction must be issued before a page program, sector erase, chip erase or write status register i nstruction will be accepted. after completing a program, erase or write instruction the write enabl e latch (wel) is automatically cleared to a write disabled state of 0. software controlled write protection is facilitated using the write status register instruction and se tting the status register protect (srp) and block protect (tb, bp2, bp1, and bp0) bits. these status register bits allow a portion or all of the memory to be configured as read only. used in conjunction with the write protect (/wp) pin, changes to the status register can be enabled or disabled under hardware control. see status register for further informatio n. additionally, the powerdown instruction offers an extra level of write protection as all instructions are ignored except for the release powerdown instructi on.
w25x64 - 12 - 10 control and status registers the read status register instruction can be used to provide status on the availability of the flash memory array, if the device is write enabled or dis abled, and the state of write protection. the write status register instruction can be used to configur e the devices write protection features. see figure 3. 10.1 status register 10.1.1 busy busy is a read only bit in the status register (s0) that is set to a 1 state when the device is execut ing a page program, sector erase, block erase, chip erase or write status register instruction. during this time the device will ignore further instructions ex cept for the read status register instruction (see t w , t pp , t se , t be , and t ce in ac characteristics). when the program, erase or write status register instruction has completed, the busy bit will be cleared to a 0 state indicating the device is ready for further instructions. 10.1.2 write enable latch (wel) write enable latch (wel) is a read only bit in the status register (s1) that is set to a 1 after execu ting a write enable instruction. the wel status bit is cle ared to a 0 when the device is write disabled. a wr ite disable state occurs upon powerup or after any of the following instructions: write disable, page program, sector erase, block erase, chip erase and write status register. 10.1.3 block protect bits (bp2, bp1, bp0) the block protect bits (bp2, bp1, and bp0) are non volatile read/write bits in the status register (s4 , s3, and s2) that provide write protection control a nd status. block protect bits can be set using the write status register instruction (see t w in ac characteristics). all, none or a portion of the memory array can be protected from program and erase instr uctions (see status register memory protection table). the factory default setting for the block p rotection bits is 0, none of the array protected. t he block protect bits can not be written to if the sta tus register protect (srp) bit is set to 1 and the write protect (/wp) pin is low. 10.1.4 top/bottom block protect (tb) the top/bottom bit (tb) controls if the block prote ct bits (bp2, bp1, bp0) protect from the top (tb=0) or the bottom (tb=1) of the array as shown in the s tatus register memory protection table. the tb bit is nonvolatile and the factory default setting is tb=0. the tb bit can be set with the write status register instruction provided that the write enable instruction has been issued. the tb bit can not be written to if the status register protect (srp) bit is set to 1 and the write protect (/wp) pin is low . 10.1.5 reserved bits status register bit location s6 is reserved for fut ure use. current devices will read 0 for this bit l ocation. it is recommended to mask out the reserved bit when te sting the status register. doing this will ensure compatibility with future devices.
w25x64 publication release date: december 19, 2008 - 13 - revision a 10.1.6 status register protect (srp) the status register protect (srp) bit is a nonvola tile read/write bit in status register (s7) that ca n be used in conjunction with the write protect (/wp) pi n to disable writes to status register. when the sr p bit is set to a 0 state (factory default) the /wp p in has no control over status register. when the sr p pin is set to a 1, the write status register instructio n is locked out while the /wp pin is low. when the /wp pin is high the write status register instruction i s allowed. figure 3. status register bit locations 10.1.7 status register memory protection status register (1) w25x64 (64m-bit) memory protection tb bp2 bp1 bp0 block(s) addresses density portion x 0 0 0 none none none none 0 0 0 1 126 and 127 7e0000h 7fffffh 128kb upper 1 /64 0 0 1 0 124 and 127 7c0000h 7fffffh 256kb upper 1 /32 0 0 1 1 120 thru 127 780000h 7fffffh 512kb upper 1/16 0 1 0 0 112 thru 127 700000h 7fffffh 1mb upper 1/ 8 0 1 0 1 96 thru 127 600000h 7fffffh 2mb upper 1/4 0 1 1 0 64 thru 127 400000h 7fffffh 4mb upper 1/2 1 0 0 1 0 and 1 000000h 01ffffh 128kb lower 1/64 1 0 1 0 0 thru 3 000000h 03ffffh 256kb lower 1/32 1 0 1 1 0 thru 7 000000h 07ffffh 512kb lower 1/16 1 1 0 0 0 thru 15 000000h C 0fffffh 1mb lower 1/8 1 1 0 1 0 thru 31 000000h C 1fffffh 2mb lower 1/4 1 1 1 0 0 thru 63 000000h C 3fffffh 4mb lower 1/2 x 1 1 1 0 thru 127 000000h 7fffffh 8mb all note: 1. x = dont care
w25x64 - 14 - 10.2 instructions the instruction set of the w25x64 consists of fifte en basic instructions that are fully controlled thr ough the spi bus (see instruction set table). instructio ns are initiated with the falling edge of chip sele ct (/cs). the first byte of data clocked into the dio input provides the instruction code. data on the di o input is sampled on the rising edge of clock with m ost significant bit (msb) first. instructions vary in length from a single byte to s everal bytes and may be followed by address bytes, data bytes, dummy bytes (dont care), and in some c ases, a combination. instructions are completed with the rising edge of edge /cs. clock relative ti ming diagrams for each instruction are included in figures 4 through 19. all read instructions can be completed after any clocked bit. however, all instructions that write, program or erase must comp lete on a byte boundary (cs driven high after a ful l 8bits have been clocked) otherwise the instruction will be terminated. this feature further protects the device from inadvertent writes. additionally, while the memory is being programmed or erased, or when the status register is being written, all instructi ons except for read status register will be ignored until the program or erase cycle has completed. 10.2.1 manufacturer and device identification manufacturer id (m7-m0) winbond serial flash efh device id (id7-id0) (id15-id0) instruction abh, 90h 9fh w25x64 16h 3017h
w25x64 publication release date: december 19, 2008 - 15 - revision a 10.2.2 instruction set (1) instruction name byte 1 code byte 2 byte 3 byte 4 byte 5 byte 6 n-bytes write enable 06h write disable 04h read status register 05h (s7Cs0) (1) (2) write status register 01h s7Cs0 read data 03h a23Ca16 a15Ca8 a7Ca0 (d7Cd0) (next by te) continuous fast read 0bh a23Ca16 a15Ca8 a7Ca0 dummy (d7Cd0) (next byte) continuous fast read dual output 3bh a23Ca16 a15Ca8 a7Ca0 dummy i/o = (d6,d4,d2,d0) o = (d7,d5,d3,d1) (one byte per 4 clocks, continuous) page program 02h a23Ca16 a15Ca8 a7Ca0 (d7Cd0) (nex t byte) up to 256 bytes block erase (64kb) d8h a23Ca16 a15Ca8 a7Ca0 sector erase (4kb) 20h a23Ca16 a15Ca8 a7Ca0 chip erase c7h powerdown b9h release power down / device id abh dummy dummy dummy (id7id0) (4) manufacturer/ device id (3) 90h dummy dummy 00h (m7m0) (id7id0) jedec id 9fh (m7m0) manufacturer (id15id8) memory type (id7id0) capacity notes: 1. data bytes are shifted with most significant bit first. byte fields with data in parenthesis ( ) indicate data being read from the device on the do pin. 2. the status register contents will repeat continu ously until /cs terminates the instruction. 3. see manufacturer and device identification table for device id information. 4. the device id will repeat continuously until /cs terminates the instruction.
w25x64 - 16 - 10.2.3 write enable (06h) the write enable instruction (figure 4) sets the wr ite enable latch (wel) bit in the status register t o a 1. the wel bit must be set prior to every page prog ram, sector erase, block erase, chip erase and write status register instruction. the write enable instruction is entered by driving /cs low, shiftin g the instruction code 06h into the data input (di) pin on the rising edge of clk, and then driving /cs hi gh. figure 4. write enable instruction sequence diagram 10.2.4 write disable (04h) the write dissable instruction (figure 5) resets th e write enable latch (wel) bit in the status regist er to a 0. the write disable instruction is entered by driving /cs low, shifting the instruction code 04h into the dio pin and then driving /cs high. note that th e wel bit is automatically reset after powerup and upon completion of the write status register, page program, sector erase, block erase and chip erase instructions. figure 5. write disable instruction sequence diagra m
w25x64 publication release date: december 19, 2008 - 17 - revision a 10.2.5 read status register (05h) the read status register instruction allows the 8b it status register to be read. the instruction is entered by driving /cs low and shifting the instruc tion code 05h into the dio pin on the rising edge of clk. the status register bits are then shifted out on the do pin at the falling edge of clk with most significant bit (msb) first as shown in figure 6. t he status register bits are shown in figure 3 and i nclude the busy, wel, bp2bp0, tb and srp bits (see descri ption of the status register earlier in this datasheet). the status register instruction may be used at any time, even while a program, erase or write status register cycle is in progress. this allows the busy status bit to be checked to determine when the cycle is complete and if the device can accept anot her instruction. the status register can be read continuously, as shown in figure 6. the instruction is completed by driving /cs high. figure 6. read status register instruction sequence diagram
w25x64 - 18 - 10.2.6 write status register (01h) the write status register instruction allows the st atus register to be written. a write enable instruc tion must previously have been executed for the device t o accept the write status register instruction (status register bit wel must equal 1). once write enabled, the instruction is entered by driving /cs low, sending the instruction code 01h, and then w riting the status register data byte as illustrated in figure 7. the status register bits are shown in fig ure 3 and described earlier in this datasheet. only nonvolatile status register bits srp, tb, bp2 , bp1 and bp0 (bits 7, 5, 4, 3 and 2) can be writte n to. all other status register bit locations are rea donly and will not be affected by the write status register instruction. the /cs pin must be driven high after the eighth bi t of the last byte has been latched. if this is not done the write status register instruction will not be e xecuted. after /cs is driven high, the selftimed w rite status register cycle will commence for a time dura tion of t w (see ac characteristics). while the write status register cycle is in progress, the read stat us register instruction may still accessed to check the status of the busy bit. the busy bit is a 1 dur ing the write status register cycle and a 0 when th e cycle is finished and ready to accept other instruc tions again. after the write register cycle has fin ished the write enable latch (wel) bit in the status regi ster will be cleared to 0. the write status register instruction allows the bl ock protect bits (tb, bp2, bp1 and bp0) to be set f or protecting all, a portion, or none of the memory fr om erase and program instructions. protected areas become readonly (see status register memory protec tion table). the write status register instruction also allows the status register protect bit (srp) t o be set. this bit is used in conjunction with the write protect (/wp) pin to disable writes to the status r egister. when the srp bit is set to a 0 state (fact ory default) the /wp pin has no control over the status register. when the srp pin is set to a 1, the writ e status register instruction is locked out while the /wp pin is low. when the /wp pin is high the write status register instruction is allowed. figure 7. write status register instruction sequenc e diagram
w25x64 publication release date: december 19, 2008 - 19 - revision a 10.2.7 read data (03h) the read data instruction allows one more data byte s to be sequentially read from the memory. the instruction is initiated by driving the /cs pin low and then shifting the instruction code 03h foll owed by a 24bit address (a23a0) into the dio pin. the cod e and address bits are latched on the rising edge o f the clk pin. after the address is received, the dat a byte of the addressed memory location will be shifted out on the do pin at the falling edge of cl k with most significant bit (msb) first. the addres s is automatically incremented to the next higher addres s after each byte of data is shifted out allowing f or a continuous stream of data. this means that the enti re memory can be accessed with a single instruction as long as the clock continues. the instruction is completed by driving /cs high. the read data instruction sequence is shown in figure 8. if a rea d data instruction is issued while an erase, progra m or write cycle is in process (busy=1) the instructi on is ignored and will not have any effects on the current cycle. the read data instruction allows clo ck rates from d.c. to a maximum of f r (see ac electrical characteristics). figure 8. read data instruction sequence diagram
w25x64 - 20 - 10.2.8 fast read (0bh) the fast read instruction is similar to the read da ta instruction except that it can operate at the highest possible frequency of f r (see ac electrical characteristics). this is accom plished by adding eight dummy clocks after the 24bit address as sh own in figure 9. the dummy clocks allow the devices internal circuits additional time for setting up th e initial address. during the dummy clocks the data value on the dio pin is a dont care. figure 9. fast read instruction sequence diagram
w25x64 publication release date: december 19, 2008 - 21 - revision a 10.2.9 fast read dual output (3bh) the fast read dual output (3bh) instruction is simi lar to the standard fast read (0bh) instruction except that data is output on two pins, do and dio, instead of just do. this allows data to be transferred from the w25x64 at twice the rate of st andard spi devices. the fast read dual output instruction is ideal for quickly downloading code f rom flash to ram upon powerup or for applications that cache codesegments to ram for execution. similar to the fast read instruction, the fast read dual output instruction can operate at the highest possible frequency of fr (see ac electrical charact eristics). this is accomplished by adding eight dummy clocks after the 24bit address as shown in figure 10. the dummy clocks allow the device's internal circuits additional time for setting up th e initial address. the input data during the dummy clocks is dont care. however, the dio pin should be hig himpedance prior to the falling edge of the first data out clock. figure 10. fast read dual output instruction sequen ce diagram
w25x64 - 22 - 10.2.10 page program (02h) the page program instruction allows up to 256 bytes of data to be programmed at previously erased to all 1s (ffh) memory locations. a write enable instr uction must be executed before the device will accept the page program instruction (status registe r bit wel must equal 1). the instruction is initiat ed by driving the /cs pin low then shifting the instruction code 02h fo llowed by a 24bit address (a23a0) and at least one data byte, into the dio pin. the /cs pin must be held low for the entire length of the instruction while data is being sent to the device. the page program instruction sequence is shown in figure 11. if an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) should be set to 0. if the last address byte is not zero, and the number of clocks exceed the remaining page length, the addressing will wrap to the beginning of the page. in some cases, less than 256 bytes (a partial page) can be programmed withou t having any effect on other bytes within the same page. one condition to perform a partial page progr am is that the number of clocks can not exceed the remaining page length. if more than 256 bytes are s ent to the device the addressing will wrap to the beginning of the page and overwrite previously sent data. as with the write and erase instructions, the /cs p in must be driven high after the eighth bit of the last byte has been latched. if this is not done the page program instruction will not be executed. after /c s is driven high, the selftimed page program instructio n will commence for a time duration of tpp (see ac characteristics). while the page program cycle is i n progress, the read status register instruction ma y still be accessed for checking the status of the bu sy bit. the busy bit is a 1 during the page program cycle and becomes a 0 when the cycle is finished an d the device is ready to accept other instructions again. after the page program cycle has finished th e write enable latch (wel) bit in the status register is cleared to 0. the page program instruct ion will not be executed if the addressed page is protected by the block protect (bp2, bp1, and bp0) bits (see status register memory protection table). figure 11. page program instruction sequence diagra m
w25x64 publication release date: december 19, 2008 - 23 - revision a 10.2.11 sector erase (20h) the sector erase instruction sets all memory within a specified sector (4kbytes) to the erased state of all 1s (ffh). a write enable instruction must be ex ecuted before the device will accept the sector era se instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pi n low and shifting the instruction code 20h followed a 24bit sector address (a23a0) (see figure 2). the sector erase instruction sequence is shown in figur e 12. the /cs pin must be driven high after the eighth bi t of the last byte has been latched. if this is not done the sector erase instruction will not be executed. after /cs is driven high, the selftimed sector era se instruction will commence for a time duration of t se (see ac characteristics). while the sector erase cycle is in progress, the read status register inst ruction may still be accessed for checking the stat us of the busy bit. the busy bit is a 1 during the sec tor erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other in structions again. after the sector erase cycle has finished the write enable latch (wel) bit in the st atus register is cleared to 0. the sector erase instruction will not be executed if the addressed p age is protected by the block protect (tb, bp2, bp1 , and bp0) bits (see status register memory protectio n table). figure 12. sector erase instruction sequence diagra m
w25x64 - 24 - 10.2.12 block erase (d8h) the block erase instruction sets all memory within a specified block (64kbytes) to the erased state o f all 1s (ffh). a write enable instruction must be ex ecuted before the device will accept the block eras e instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pi n low and shifting the instruction code d8h followed a 24bit block address (a23a0) (see figure 2). the block erase instruction sequence is shown in figure 13. the /cs pin must be driven high after the eighth bi t of the last byte has been latched. if this is not done the block erase instruction will not be executed. a fter /cs is driven high, the selftimed block erase instruction will commence for a time duration of t be (see ac characteristics). while the block erase cycle is in progress, the read status register inst ruction may still be accessed for checking the stat us of the busy bit. the busy bit is a 1 during the blo ck erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other in structions again. after the block erase cycle has finished the write enable latch (wel) bit in the st atus register is cleared to 0. the block erase instruction will not be executed if the addressed p age is protected by the block protect (tb, bp2, bp1 , and bp0) bits (see status register memory protectio n table). figure 13. block erase instruction sequence diagram
w25x64 publication release date: december 19, 2008 - 25 - revision a 10.2.13 chip erase (c7h) the chip erase instruction sets all memory within t he device to the erased state of all 1s (ffh). a wr ite enable instruction must be executed before the devi ce will accept the chip erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting t he instruction code c7h. the chip erase instruction sequence is shown in figure 14. the /cs pin must be driven high after the eighth bi t has been latched. if this is not done the chip er ase instruction will not be executed. after /cs is driv en high, the selftimed chip erase instruction will commence for a time duration of t ce (see ac characteristics). while the chip erase cyc le is in progress, the read status register instruction may still be accessed to check the status of the busy bit. the busy bit is a 1 during the chip erase cycl e and becomes a 0 when finished and the device is ready to accept other instructions again. after the chip erase cycle has finished the write enable lat ch (wel) bit in the status register is cleared to 0. t he chip erase instruction will not be executed if a ny page is protected by the block protect (bp2, bp1, a nd bp0) bits (see status register memory protection table). figure 14. chip erase instruction sequence diagram
w25x64 - 26 - 10.2.14 power-down (b9h) although the standby current during normal operatio n is relatively low, standby current can be further reduced with the powerdown instruction. the lower power consumption makes the powerdown instruction especially useful for battery powered a pplications (see icc1 and icc2 in ac characteristic s). the instruction is initiated by driving the /cs pin low and shifting the instruction code b9h as sho wn in figure 15. the /cs pin must be driven high after the eighth bi t has been latched. if this is not done the powerd own instruction will not be executed. after /cs is driv en high, the powerdown state will entered within t he time duration of t dp (see ac characteristics). while in the powerdown state only the release from powerdown / device id instruction, which restores the device to normal operation, will be recognized. all other instructions are ignored. this includes the r ead status register instruction, which is always available during normal operation. ignoring all but one instruction makes the power down state a usefu l condition for securing maximum write protection. th e device always powersup in the normal operation with the standby current of icc1. figure 15. deep pow erdow n instruction sequence dia gram
w25x64 publication release date: december 19, 2008 - 27 - revision a 10.2.15 release power-down / device id (abh) the release from powerdown / device id instruction is a multipurpose instruction. it can be used to release the device from the powerdown state, obtai n the devices electronic identification (id) number or do both. when used only to release the device from the power down state, the instruction is issued by driving t he /cs pin low, shifting the instruction code abh an d driving /cs high as shown in figure 16. after the time duration of t res1 (see ac characteristics) the device will resume no rmal operation and other instructions will be accepted. the /cs pin must remain high duri ng the t res1 time duration. when used only to obtain the device id while not in the powerdown state, the instruction is initiated by driving the /cs pin low and shifting the instructio n code abh followed by 3dummy bytes. the device id bits are then shifted out on the falling edge of cl k with most significant bit (msb) first as shown in figure 17. the device id value for the w25x64 is listed in manufacturer and device identification table. the device id can be read continuously. the instruction is completed by driving /cs high. when used to release the device from the powerdown state and obtain the device id, the instruction is the same as previously described, and shown in figu re 17, except that after /cs is driven high it must remain high for a time duration of t res2 (see ac characteristics). after this time duration the device will resume normal operation and other instructions will be accepted. if the release from powerdown / device id instruct ion is issued while an erase, program or write cycl e is in process (when busy equals 1) the instruction is ignored and will not have any effects on the cur rent cycle figure 16. release pow erdow n instruction sequence
w25x64 - 28 - figure 17. release pow erdow n / device id instructi on sequence diagram note: ** see section 10.2.1
w25x64 publication release date: december 19, 2008 - 29 - revision a 10.2.16 read manufacturer / device id (90h) the read manufacturer/device id instruction is an a lternative to the release from powerdown / device id instruction that provides both the jedec assigne d manufacturer id and the specific device id. the read manufacturer/device id instruction is very similar to the release from powerdown / device id instruction. the instruction is initiated by drivin g the /cs pin low and shifting the instruction code 90h followed by a 24bit address (a23a0) of 000000h. a fter which, the manufacturer id for winbond (efh) and the device id are shifted out on the falling ed ge of clk with most significant bit (msb) first as shown in figure 18. the device id value for the w25x64 is listed in manufacturer and device identification t able. if the 24bit address is initially set to 000001h t he device id will be read first and then followed b y the manufacturer id. the manufacturer and device ids ca n be read continuously, alternating from one to the other. the instruction is completed by driving /cs high. figure 18. read manufacturer / device id diagram note: ** see section 10.2.1
w25x64 - 30 - 10.2.17 jedec id (9fh) for compatibility reasons, the w25x64 provides seve ral instructions to electronically determine the identity of the device. the read jedec id instructi on is compatible with the jedec standard for spi compatible serial memories that was adopted in 2003 . the instruction is initiated by driving the /cs pin low and shifting the instruction code 9fh. the j edec assigned manufacturer id byte for winbond (efh) and two device id bytes, memory type (id15id8) and capacity (id7id0) are then shifted out on the fall ing edge of clk with most significant bit (msb) fir st as shown in figure 19. for memory type and capacity va lues refer to manufacturer and device identificatio n table. figure 19. read jedec id
w25x64 publication release date: december 19, 2008 - 31 - revision a 11 electrical characteristics 11.1 absolute maximum ratings (1) parameters symbo l conditions range unit supply voltage vcc C0.6 to +4.0 v voltage applied to any pin v io relative to ground C0.6 to vcc +0.4 v transient voltage on any pin v iot <20ns transient relative to ground C2.0v to vcc+2.0v v storage temperature t stg C65 to +150 c lead temperature t lead see note (2) c electrostatic discharge voltage v esd human body model (3) C2000 to +2000 v notes: 1. this device has been designed and tested for the specified operation ranges. proper operation outside of these levels is not guaranteed. exposure to absolute maximum ratings may affect device reliability. exposure beyond absolute maximum ratin gs may cause permanent damage. 2. compliant with jedec standard jstd20c for smal l body snpb or pbfree (green) assembly and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu. 3. jedec std jesd22a114a (c1=100 pf, r1=1500 ohms, r2=500 ohms). 11.2 operating ranges spec parameter symbol conditions min max unit supply voltage vcc f r = 75mhz, f r = 33mhz 2.7 3.6 v ambient temperature, operating t a industrial C40 +85 c
w25x64 - 32 - 11.3 power-up timing and write inhibit threshold spec parameter symbol min max unit vcc (min) to /cs low t vsl (1) 10 s time delay before write instruction t puw (1) 1 10 ms write inhibit threshold voltage v wi (1) 1 2 v note: 1. these parameters are characterized only. figure 20. pow erup timing and voltage levels
w25x64 publication release date: december 19, 2008 - 33 - revision a 11.4 dc electrical characteristics spec parameter symbol conditions min typ max unit input capacitance c in (1) v in = 0v (2) 6 pf output capacitance cout (1) v out = 0v (2) 8 pf input leakage i li 2 a i/o leakage i lo 2 a standby current i cc 1 /cs = vcc, vin = gnd or vcc 25 50 a powerdown current i cc 2 /cs = vcc, vin = gnd or vcc <1 10 a current read data / dual output read 1mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 5/6 7/8 ma current read data / dual output read 33mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 7/8 11/12 ma current read data / dual output read 50mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 9/10 13/15 ma current read data / dual output read 75mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 11/12 16/18 ma current page program i cc 4 /cs = vcc 20 25 ma current write status register i cc 5 /cs = vcc 10 18 ma current sector/block erase i cc 6 /cs = vcc 20 25 ma current chip erase i cc 7 /cs = vcc 20 25 ma input low voltage v il C0.5 vcc x 0.3 v input high voltage v ih vcc x0.7 vcc +0.4 v output low voltage v ol i ol = 1.6 ma 0.4 v output high voltage v oh i oh = C100 a vcc C0.2 v notes: 1. tested on sample basis and specified through des ign and characterization data. ta=25 c, vcc 3v.
w25x64 - 34 - 2. checker board pattern.
w25x64 publication release date: december 19, 2008 - 35 - revision a 11.5 ac measurement conditions spec parameter symbol min max unit load capacitance load capacitance for fr 1 only c l 30 15 pf input rise and fall times t r , t f 5 ns input pulse voltages v in 0.2 vcc to 0.8 vcc v input timing reference voltages in 0.3 vcc to 0.7 vcc v output timing reference voltages o ut 0.5 vcc to 0.5 vcc v note: 1. output hiz is defined as the point w here data o ut is no longer driven. figure 21. ac measurement i/o waveform
w25x64 - 36 - 11.6 ac electrical characteristics spec description symbol alt min typ max unit clock frequency for all instructions, except read data (03h) 2.7v3.6v vcc & industrial temperature f r f c d.c. 75 mhz clock freq. read data instruction 03h f r d.c. 33 mhz clock high, low time, for fast read (0bh, 3bh) / other instructions except read data (03h) t clh , t cll (1) 6/7 ns clock high, low time for read data (03h) instruction t crlh , t crll (1) 8 ns clock rise time peak to peak t clch (2) 0.1 v/ns clock fall time peak to peak t chcl (2) 0.1 v/ns /cs active setup time relative to clk t slch t css 5 ns /cs not active hold time relative to clk t chsl 5 ns data in setup time t dvch t dsu 2 ns data in hold time t chdx t dh 5 ns /cs active hold time relative to clk t chsh 5 ns /cs not active setup time relative to clk t shch 5 ns /cs deselect time (for array read array read / erase or program read status register) t shsl t csh 50/100 ns output disable time t shqz (2) t dis 7 ns clock low to output valid 2.7v3.6v / 3.0v3.6v t clqv t v 7 / 6 ns output hold time t clqx t ho 0 ns continued C next page
w25x64 publication release date: december 19, 2008 - 37 - revision a 11.7 ac electrical characteristics (contd) spec description symbol alt min typ max unit /hold active setup time relative to clk t hlch 5 ns /hold active hold time relative to clk t chhh 5 ns /hold not active setup time relative to clk t hhch 5 ns /hold not active hold time relative to clk t chhl 5 ns /hold to output lowz t hhqx (2) t lz 7 ns /hold to output highz t hlqz (2) t hz 12 ns write protect setup time before /cs low t whsl (3) 20 ns write protect hold time after /cs high t shwl (3) 100 ns /cs high to powerdown mode t dp (2) 3 s /cs high to standby mode without electronic signature read t res 1 (2) 3 s /cs high to standby mode with electronic signature read t res 2 (2) 1.8 s write status register time t w 10 15 ms byte program time (first byte) (4) t bp1 30 50 s additional byte program time (after first byte) (4) t bp2 6 12 s page program time t pp 1.6 3 ms sector erase time (4kb) t se 150 300 ms block erase time (64kb) t be .8 2 s chip erase time w25x64 t ce 25 40 s notes: 1. clock high + clock low must be less than or equa l to 1/f c . 2. value guaranteed by design and/or characterizati on, not 100% tested in production. 3. only applicable as a constraint for a write stat us register instruction w hen sector protect bit is set to 1. 4. for multiple bytes after first byte w ithin a pag e, t bpn = t bp1 + t bp2 * n (typical) and t bpn = t bp1 + t bp2 * n (max), w here n = number of bytes programmed.
w25x64 - 38 - 11.8 serial output timing 11.9 input timing 11.10 hold timing
w25x64 publication release date: december 19, 2008 - 39 - revision a 12 package specification 12.1 8-pin pdip 300-mil (package code da) millimeters inches symbol min typ. max min typ. max a 5.33 0.210 a1 0.38 0.015 a2 3.18 3.30 3.43 0.125 0.130 0.135 b 0.41 0.46 0.56 0.016 0.018 0.022 b1 1.47 1.52 1.63 0.058 0.060 0.064 c 0.20 0.25 0.36 0.008 0.010 0.014 d 9.02 9.27 10.16 0.355 0.365 0.400 e 7.37 7.62 7.87 0.290 0.300 0.310 e1 6.22 6.35 6.48 0.245 0.250 0.255 e1 2.29 2.54 2.79 0.090 0.100 0.110 l 2.92 3.30 3.81 0.115 0.130 0.150 0 7 15 0 7 15 e a 8.51 9.02 9.53 0.335 0.355 0.375 s 1.14 0.045 a d 1 4 b b1 8 5 a1 e a l e1 a2 seating plane base plane s e1 e c
w25x64 - 40 - 12.2 8-contact 8x6mm wson (package code ze) millimeters inches symbol min typ. max min typ. max a 0.70 0.75 0.80 0.0276 0.0295 0.0315 a1 0.00 0.02 0.05 0.0000 0.0008 0.0019 b 0.35 0.40 0.48 0.0138 0.0157 0.0189 c 0.19 .0.20 0.25 0.0075 0.0079 0.0098 d 7.90 8.00 8.10 0.3110 0.3150 0.3189 d2 4.60 4.65 4.70 0.1811 0.1831 0.1850 e 5.90 6.00 6.10 0.2323 0.2362 0.2402 e2 5.15 5.20 5.25 0.2028 0.2047 0.2067 e 1.27 bsc 0.0500 bsc l 0.45 0.50 0.55 0.0177 0.0197 0.0217 m e ta l pa d a r e a (4 ) e d l e b d 2 e 2 a 1 c
w25x64 publication release date: december 19, 2008 - 41 - revision a 12.3 16-pin soic 300-mil (winbond package code sf) millimeters inches symbol min max min max a 2.36 2.64 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.18 0.28 0.007 0.011 d (3) 10.08 10.49 0.397 0.413 e 10.01 10.64 0.394 0.419 e1 (3) 7.39 7.59 0.291 0.299 e (2) 1.27 bsc 0.050 bsc l 0.39 1.27 0.015 0.050 0 o 8 o 0 o 8 o y 0.076 0.003 notes: 1. controlling dimensions: inches, unless otherwise specified. 2. bsc = basic lead spacing between centers.
w25x64 - 42 - 3. dimensions d and e1 do not include mold flash pr otrusions and should be measured from the bottom of the package. 13 ordering information (1) notes: 1a. only the 2 nd letter is used for the part marking; wson package type ze is not used for the top marking. 1b. standard bulk shipments are in tube (shape e). please specify alternate packing method, such as tape and reel (shape t), when placing orders. 1c. the w prefix is not included on the part mar king. 64 = 64mbit v = 2.7v to 3.6v sf = 16pin soic 300mil da = 8pin dip 300mil ze = 8pad wson 8x6mm g or z = green package (leadf ree, rohs compliant, halogenf ree(tbba ), a ntimonyoxidef ree sb 2 o 3 )
w25x64 publication release date: december 19, 2008 - 43 - revision a valid part numbers and top side marking: the following table provides the valid part numbers for the 25x64 spiflash memory. please contact winbond for specific availability by density and package t ype. winbond spiflash memories use an 11 digit product number for ordering. however, due to limited space, the top side marking on all packages use an abbreviated 9digit number. package type density product number top side markin g sf soic16 300mil 64mbit W25X64Vsfig 25x64vfig ze wson8 8x6mm 64mbit W25X64Vzeig 25x64vig da pdip8 300mil 64mbit W25X64Vdaiz 25x64vaiz notes: 1. for wson packages, the package type ze are not u sed in the top side marking.
w25x64 - 44 - 14 revision history version date page description a 12/19/08 new create trademarks winbond and spiflash are trademarks of winbond electronics corporation. all other marks are the property of their respectiv e owner. important notice winbond products are not designed, intended, author ized or warranted for use as components in systems or equipment intended for surgical implanta tion, atomic energy control instruments, airplane o r spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond prod ucts are not intended for applications wherein failure o f winbond products could result or lead to a situat ion wherein personal injury, death or severe property o r environmental damage could occur. winbond customers using or selling these products for use i n such applications do so at their own risk and agr ee to fully indemnify winbond for any damages resultin g from such improper use or sales. information in this document is provided solely in connection with winbond products. winbond reserves the right to make changes, corrections, modificatio ns or improvements to this document and the products and services decribed herein at any time, without notice.

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